Multiple input binary-coded decimal adders and subtracters



Feb. 2, 1960 J. v. BLANKENBAKER 2,923,474

MULTIPLE INPUT BINARY-CODE!) DECIMAL ADDERS AND SUBTRACTERS Filed Sept.2, 1955 4 Sheets-Sheet 1 Feb. 2, 1960 J. v. BLANKENBAKER 2,923,474

MULTIPLE INPUT BINARY-CODED DECIMAL ADDERS AND SUBTRACTERS Filed Sept.2, 1953 4 Sheets-Sheet 2 Feb. 2, 1960 BLANKENBAKER 2,923,474

V. MULTIPLE INPUT BINARY-CODED DECIMAL ADDERS AND SUBTRACTERS FiledSept. 2, 1953 4 Sheets-Sheet 4 IN V EN TOR.

BY W

United States Patent MULTIPLE INPUT BINARY-CODED DECIIVIAL ADDERS ANDSUBTRACTERS John Virgil Blankenbaker, Los Angeles, Calif., assignor, bymesne assignments, to Hughes Aircraft Company, a corporation of DelawareApplication September 2, 1953, Serial No. 378,116 13 Claims. (Cl.235-170) This invention relates to multiple input. binary-coded decimaladders and subtracters and, more particularly, to electronic multipleinput adders and subtracters wherein a single binary-coded decimalcorrection is performed upon signals representing the input variables.

The general principles of the design of binary-coded arithmetic unitsare described in at least two copending US. patent applications. In thefirst copending US. patent application, Serial No. 278,408, forArithmetic Units for Decimal-Coded Binary Computers, by Daniel L.Curtis, filed March- 25, 1952, serial and parallel arithmetic units areconsidered, each of the several embodiments disclosed including acorrection control network which produces a control signal when the truebinary result is not in the desired binary-coded decimal form. Acorrection transfer circuit, responsive to the control signal, isutilized to correct the true binary result to the desired binary-codeddecimal form when the necessity for a correction is indicated by thecontrol signal.

In the second copending U.S.' patent application, Serial No. 322,665,for Serial Arithmetic Units for Binary- Coded Decimal Computers, by E.C. Nelson, filed November 26, 1952, issued February 18, 1958, as PatentNo. 2,823,855; improved circuits for correcting the true binary resultto the desired decimal result are disclosed. The feature of thesecircuits is that the true binary result is shifted and corrected in asingle operation, making it possible to reduce the amount of storagecapacity required to record the numbers as well as the amount of timerequired in adding or subtracting input numbers.

A class of correction circuits has been produced wherein thebinary-coded decimal corrections are formed directly as a function ofbinary carry signals C and C, and complementary comparison signals Q andQ, where signal Q is defined as one having a l-representing level whenthe carry signal is equal to the desired true binary result. In thesecircuits, the result-from-carry technique makes it possible to performthe binary-coded decimal correction on a time-sharing basis such that itis possible to considerably reduce the number of gating elementsrequired.

Since each addition or subtraction of binary-coded decimal numbers in atwo-input adder or subtracter of the type described in theabove-mentioned copending applications requires a separate correctionnetwork, it is apparent that a multiple input adder including aplurality of two input adders requires a considerable number ofcorrection flip-flops and corresponding gating circuits. For example, inorder to add three binary-coded input signals simultaneously, the adderrequires two 2-input binary-coded decimal adders and, consequently, fourcorrection flip-flops as well as six flip-flops for the input signalsand binary carries. In addition, if it is desired to obtain the simplegating circuit technique of the resultfrom-carry type of adder describedabove, two additional comparison flip-flops or, in any event, two bufferflip-flop stages are required. As a result of the number ofseriesconnected flip-flops required, the summing process requires twiceas long as the time required to sum two result is formed through asingle correction circuit requiring only two flip-flops. In oneembodiment of the present invention three binary-coded input signals aresimultaneously added and then corrected in a single operationintroducing a time delay of only 5 or 6 binary digit time intervals, theentire circuit requiring only 10 flip-flops or trigger circuits. A3-input adder comprising two Z-input adders, on the other hand, requires12flipflops, including two buffer or comparison stages, and introduces atime delay of 8 binary digit time intervals during operation.

The second copending application contains a considerable amount ofdescription concerning the logical design of shifting and correctingnetworks either based upon a true binary result to decimal resultconversion or upon a conversion made as a function of the binary carryseries, and signals of a comparison flip-flop. Consequent- 1y, it isconvenient to incorporate this application into the presentspecification by way of frequent reference. The second copendingapplication is referred to as the above-mentioned copending applicationto E. C. Nelson.

In the ensuing description of the multiple-input binarycoded decimaladders and subtracters of the present invention, reference is frequentlymade to binary carryover-one, binary carry-over-two, decimalcarry-over-one, and decimal carry-over-two digit signals. For purposesof clarity in the ensuing description, these terms are herewith defined.A binary carry-over-one is a conventional binary carry and is hereindefined as a unit carryover to the next higher order binary digitalplace resulting from the performance of an arithmetic operation on thebinary digits of a given binary digital place of two or more binarynumbers. A binary carry-over-two is defined as a two-unit carry-over tothe next higher order binary digital place resulting from the arithmeticoperation on the binary digits in the given binary digital place of thebinary numbers. A decimal carry -over-one and a decimal carry-over-twoare defined as a unit carry-over and a two-unit carry-over,respectively, to the next higher order digital place in a decimal systemresulting from the performance of an arithmetic operation on decimaldigits in a given decimal digital place of two or more decimal numbers.V

Accordingly it is an object of the present invention to provide amultiple input binary-coded decimal adder or subtracter requiring only asingle correction circuit for converting the true binary result of anoperation to the desired binary-coded decimal result.

Another object is to provide a multiple input binary- I coded decimalinput adder or subtracter for producingthe desired decimal result in:asingle correction operation,

thereby eliminating additional operating time for subv sequentcorrections.

Still another object is to provide a multiple input binary-coded decimaladder-subtracter requiring fewer flip-flop or trigger circuits than theequivalent addersubtracter comprising a number of 2-input binary-codeddecimal adder-subtracters. v

The novel features which are believed to be characteristic of theinvention, both as to its organization and method of operation, togetherwith further objects and advantages thereof, will, be better understoodfrom the following description considered in connection with theaccompanying drawings in which several embodiments of the invention areillustrated by way of examples. It is to be expressly understood,however, that the drawings a s t- 4 i are for the purpose-ofillustrationand description only, and are not intended as a definitionof the limits of the invention. V

1' tz Fig. L is a s'chematic diagram of a'G-inputbihziryi'coded':decimal t adder according to 'the present invention wherein the truebinary-sum Sh is produced-as a func- 'tion of carrysignals' C and Crepresenting carries over "one-and two time intervals, respectively.

' Fig. 2 is a schematic circuit diagrambf the directcurrenttrigger-circuit F (1,3), of Figfl;

Figs-3 and 3a present a schematic circuit'diagram an a symbolicrepresentation, respectively, of a typicalfiip- *lflop circuit suitablefor use inrhe meenanizanonbr the present invention. l H

Figs. '4 and 4a present a"sehematicl' circ'uit "diagram 'anda voltagewaveform chart, re's'peetively,"o-a typical eomplementer {circuitsuitable "for use in the mechaniza- "tion' of the present invention. l

Figs. 5 and 5a present a schematic ciictiit'diagramjand asymbolicrepresentation, respectively, 'o'f atypical logical 1 andcircuitsuitable for use in the mechanization "of "the presentjinvention. v 7

Figs. 6 and 6a present a schematic circuit diagram and asymbolicrepresentation, respectively, of a typical logical or circuit suitablefor use .in the mechaniiationof the present invention. a

Reference is now niade'to Fig. 1 wherein there is presented a 3-inputbinary-coded-rdecimal adder accord- -ing to the present invention.'Asshownin Fig.- 1, the 3- input adder is responsive to threepairs ofcomplementary binary input signals A, A; B, 1 3; and X/X; produced by3-input means A, B, and X, respectively, representing three binary-codeddecimal input numbers, and is responsive to synchronizing or'clockpulses Cp and decimal correction timing signals T and 'I for producingbinary output. signals Sd representing the arithmetic sum of the3'-input"numbersiin binary-coded decimal form.

A binary-coded decimal number is hereindefined as a decimal numberwherein each decimal digit is repre- 'sented by a group of binary digitshaving pre-assigned weights, For example, in a conventional binary-codeddecimal system, four binary digits are utilized to represent eachdecimal digit wherein the four binary digits have weights of 1, 2, '4,and 8 for the least, second-tofleast,second-to-rnost, and mostsignificant binary digit, respectively, representing each decimal digit.A true binary number, on the other hand, is hereindefined inftheconventional manner as a number comprised of a fsinglegroup ofbinary digits, each binary digit having a weight twice the weight of thenext lower-order binary digit in the group with the least significantbinary digit fof the" group havingia weight of 1. Thus, by way of'example,'the "decimal number 37 is expressedin' the 1, 2,4; 8binary-coded decimal number system as two groups of four binary digits,thus: 0111 andOOll representing the decimal digit 7 and 3, respectively;whereas in true 'binary form the number 37 is represented by a single'group of binary digits thus 100101 Each-of the above groups of binarydigits is written'inthe order of most "significant binary digit on theeXtreme left hand end of the group and progressively writingfthe binarydigits of decreasing weight until the least significant binary digit,having a weight oil is written at the extremeright hand end of thegroup. 1

For purposes of illustrating the presentinvention, it is assumed thateach of the three decimahinput numbers r p' s' fi b 1s.A;5; B; 1' d X,espe ilyjisCdded'in the conventionallj'2, 4, 8binary-coded*decimahsystem above described; ,In additionyit is assumed that eachinput number "is'serially received in lithe order of least significantdecimal digitfirlstandmost significant decimai digit last, and furtherthat each' decianal digit isfrepresented 'by ,four binary digitsreceived inthe'order or least significant nast 'digit, first and i l lieein si na s F and, and fl ti m di e a hat or 2:

most significant binary digit last. It is further assumed that eachbinary digit of anumber is represented by a two-level or binaryelectrical signal having a relatively high signal value inrepresentation of a binary l and a relatively low signal value inrepresentation of a binary 0. A bar over a signal "indicates thecomplement of hev alt-n .l .r r .r l .v t n Thus, input means A,of Fig.,li,pr oduc es a' relatively high or 1 level signal A and a relativelylow or 0 level signal 1 "in'fi'epires',en tion ofi 'af binary 1 digit,Conversely, a binaryT) digifis' represeuted jby a relatively low or 0level signal A and a relatively high or 1 level signal A. In a similarmanner each' binary digit "produced by input means B and o f; tl tefigureare similarly represented by signals B, 1 3; and X, K;respectively.

The signals produced by input means A, Brand X are @mbi i w ga i -m an19am) d 0F f the input digits produced by means gfir B and xare binary}and that 2 or 3 of the input digits'produced bymeans A, B, and X re inam-a T e-s a F 1? P! QQdI Y.,g t ng means I 101305) are a li ddire yst a tstzcun tt l ge circuit i e). which P d 5 c r es on n .wcomp c t ysignals F F the signals ;heingl produced "without any delay. rThevsignals F 3 andifi fiiproduced: by gating means 10F(2,3),.areaappliedjto: aZ-flip-flop circuit F(2,3) producing correspondingcomplementary. signals F and F correspondingto the input-signals delayedby lt-binarydigit time interval; irepre'senting the binary digitposition with respect toinput signals *A-,-*B, and X;

'In. addition to the above describedrgating.circuits, the embodiment ofFigsl furtheniincludes a plurality of-gat ing circuits 10(31, 4062,1ai1d.10Sb, respectively controlling a' plurality .offlip-flops C1, C2,,andsbiprodu'cing signals correspondingi to the t'rue'b'inarycarry=over-one series Q the true binary'carry-o'ver two' series C5 andthe true binary carry suin'serieslSb; the subscript again indicating thedigit position with respect to the input signals. t r

Since, as hasbeen previouslyrmentioned, the value 'of each*binary digitinafqlr, 2, 4L8,.binary 'codedhdecimal "system hasa weighthdouble ,that'ofithe binary digit in the immediately ,preceding'lesser;significantbinary place,

a carrytdigitxresulting' froinnthe additign'to two binary 1 digits hasaweightidoublet ih dtnqfs3611,Qf the binary digits from which it isfQrmed-n Morespecifically, if, a

time t am. h esl it a 9t tw bi y digits a eight oii ene the carrrepresents a weight lierefore, if two brna ded deciinal numco esporidingbinary digi ii h ir'iost' significant corresponding binary; digitslast,, a,srngle carry signal is sulficien tu For "example, i f'twohinary ldi'gits, each having a weight'oftwmiare added togetherlthetotal'weight of thesum will be four' as re resented by ab inary 0 sumdigit and a binary lucarry digit. {The binary I carry,

digit is then added rains binarydigit sfin'fthe next succeedinghigher'order binary digit," place or the two numbers being added;thebinary'digits of the, next succeeding :higher, order having'weightsof ffoiir, wever,'where anda sing e, carry binary ;IdiQiL fOn theunex"succeed f'ingfaddion;periodyhowever, foul: hi'narydigits must besimultaneouslyadded,;iIe.,/the"three binary 'digits representing'thefthreeinp utfnu bers dthe carrydigit. This means that twofela'sses 9f rysignalsmustbe developed :for aLl-inputaddsaffit t car yf v ng a ws t uare produced. indisecond carry having a weight double that of the firstcarry or four times that of each binary digit added. The first carryisconventionally referred to as the carry-overone, and the second carryas the carryover-two; the above terminology being utilized herein.

The 3-input binary-coded decimal adder of Fig. 1 also includes a gatingcircuit 10Cd for producing decimal carry signals controlling a flip-flopCd a binary-coded decimal correction circuit (not specifically indicatedas such in the figure) comprising a pair of flip-flops F1 and F2controlled by gating circuits 10F1 and MP2, respectively, for producingcorrection signals on the output leads of flip-flops F1 and F2, and anoutput gating circuit 108d for producing output signals Sd correspondingto the binary digits of the decimal sum in binary-coded decimal form.

The output signals developed by gating circuits 105b, ldcd and 10F1 areeach applied to the input circuit of the corresponding flip-flops Sb, Cdand F1 through a separate complementer circuit C0. Each of thecomplementer circuits Co is identical and is responsive to binary inputsignals impressed on a first input lead and responsive to clock ortrigger pulses Cp impressed on a second input lead for producing a firstand a second series of output pulses. The first series of output pulsesare produced by gating the input clock pulses Cp to a first output leadwhenever the binary input signals on the first input are 1 levelsignals. The second series of output pulses are produced by gating theinput pulses Cp to a second output lead whenever the input signals onthe first input lead are level signals.

The clock or trigger pulses Cp are orderly, equally spaced pulses whichare externally generated and .applied to the 3-input adder circuit ofFig. 1 for synchronizing or timing the operation of the flip-flopcircuits. More specifically, the pulses Cp are impressed on a clock busof the circuit of Fig. 1, indicated in the figure as a horizontal linewith the identifying letters Cp at the extreme left hand end of the bus.Although each flipflop is regulated or controlled by signals generatedby a corresponding gate circuit, as above indicated, this is actuallyaccomplished by selectively gating clock pulses Cp to the flip-flop bythe corresponding gating circuits, the clock pulses Cp actuallytriggering the flip-flop. This will be more fully explained later on.

Direct-current trigger F (1,3) may be any or" the Wellknown types oftrigger circuits presently utilized in the electronic art for receivingbinary or two-level voltage signals in a single input circuit,reproducing the signals on a first output circuit, and producing aninverted or complemented version of the input signals on a second outputcircuit, thus developing the original input signal and its complement onthe first and second output circuits, respectively. Such circuits areutilized for two purposes: (1) to boost or raise the power in the inputsignals for purposes of driving succeeding circuitry, and (2) to providethe complement of the input signals.

Each of the flip-flops F(2,3), C1, C2, Sb, Cd F2, and F1 is aconventional flip-flop having a l and a 0 input circuit such thatsignals applied separately to the 1 and 0 input circuits sets thefiip-fiop to stable states representing binary l and 0, respectively,and the simultaneous application of signals to both input circuitstriggers the flipfiop or causes it to change stable states.

Before considering in more detail the operation of the 3-input adder ofFig. l, and the detailed structure of the gating circuits F(1,3),10F(2,3), 10C1, 10C2, 108b, 10Cd 10F2, NFL and 108d, it is consideredadvantageous at this time to consider in more detail the struc- ,tureand operation of the direct-current trigger circuit F(1,3), theflip-flops C1, C2, Sb, Cd F2, and F1, and the complementer circuits C0.

Referring to Fig. 2, there is presented a schematic circuit diagramF(1,3) indicated by broken lines of a preferred embodiment of thedirect-current trigger F(1,3)

the complement of input signals F, The second D.C.

amplifier 401 is coupled to the first D.C. amplifier 400 and responsiveto signals F produced by D.C. amplifier 400 for developing signals F onoutput lead 405. The signals F are signals having the same phase andvoltage amplitude as the input signals F but have a greater powercapacity than input signals F i.e., are developed from a lower impedancesource. Therefore, from a voltage standpoint, output signals F are areproduction of I input signals F and output signals E are complementarysignals of input signals F The clamping circuit 402 is coupled to thefirst D.C. amplifier 400 and the second D.C. amplifier 401 for receivingcomplementary output signals F and F on leads 405 and 404, respectively,and clamping the voltage level swings of signals F and F within the samelimits as the voltage level swings of input signals F D.C. amplifier 400is a conventional direct current amplifier circuit and includes a triode410, a plate load resistor 412, a biasing battery 411, and an inputvoltage divider circuit comprised of resistors 413 and 414 in series.The input signals F appearing on lead 403 are applied to the upperextremity of the voltage divider circuit, the lower extremity of whichis connected to ground. The common junction point of resistors 413 and414 is connected to the control grid 415 of triode 410, thus by theproper choice of resistance values for resistors 413 and 414, the inputsignals F on lead 403 may be reduced to convenient voltage level swingsfor application to control grid 415. The cathode 416 of tube 410 isreturned to ground through the biasing battery 411 thus supplying aconvenient grid-cathode bias ontube 410. The anode 417 of tube 410 iscoupled to a B-|- supply through the load resistance 412. The outputlead 404 is directly coupled to the anode 417 of tube 410, thus theoutput signals F on lead 404 are developed as the output signals of theD.C. amplifier 400 developed by the load resistor 412.

D.C. amplifier 401 is substantially identical to D.C. amplifier 400above described in that signals F3 developed by amplifier 400 on lead404 are applied to a control grid 420 of a triode tube 421 through aninput voltage divider circuit comprised of resistors 422 and 423connected in series between the input lead 404 and ground. The cathodeof tube 421 is maintained at a potential positive in relation to thecontrol grid 420 by a bias battery 425. The anode of tube 421 issupplied with a 13+ supply through a load resistor 424. The output lead405 is connected directly to the anode of tube 421 and thus signals Fappearing on lead 405 are developed as the output signals of D.C.amplifier 401.

Direct current amplifiers of the above described class are fullydescribed in Electronics Experimental Techniques by William C. Elmoreand Mathew Sands, published by McGraw-Hill Book Company, Inc., 1949,pages to 183.

The clamping circuit 402 includes a first diode clamp 430 and a seconddiode clamp 431. Diodeclamp 430 is coupled to output lead 404 forclamping output signals F within the limits between two direct-currentvoltage values E and E impressed on clamp 430, and diode clamp 431 iscoupled to lead 405 for maintaining signals F,- appearing on lead 405within the same limits in response to the voltages E and E impressedthereon. Diode clamp 430 includes a first diode 432 having its i, antdnhia 1. th'lt n 2 V ,its cathode connected 'to;,voltage E the cathodeof diode 4,32 andjthe ,anodefoffdiqde 433 ;beingco1inected comhaving 1and O inputsand' a correspon "in order 'toilliistra'te the equivalencebetween the above monly to the output lead 1404.; Thus diode clamp 430operates as atc mp nec c tf r.l mp n i n appearing Q .11 .404.b. w theampl q 'v lta of this class are: 'fullyldiscuss'd' in ffElecti'onicaExperh mental Techriiqiie's; by' willia'mf'C ,Elrfio're I and Mathew awa t ding letter therein.

circuit 900 indicated bybrolc'en" liri'essu'ita efor operation in" themultiple input binary-coded al adders andsubtricters ofthepresentinventidn. Asiridicated in the fignregtheflip-flobirduitDflflihClfidiejs'fja 1' and 0 input circuit identified by leads901" and 9 02,f're"spectively, and complementary output leads 903and-904. The fiip flop circuit of Fig; 3 [is described in detail'inU.S'.P'atent 2,644,887, entitled Synchronizing Generator byA; E. Wolfe,Jr.,"issue'd July 7,1953. Therefore, further-explan'ation of. thedetailed constructioma'ndhperation 'of the flip-flop 900'isdeernedunnecessaryfhere. Fig. 3a illustrates thecharacteristic"symbolism used throughout this description for theflip-flop 500 of Fig 3. It should benoted th'atthere is'a directcorrespondencebetween the input'andoutputterminals 901, 902,ahd 9 03,904,

respectively, of'Fig. Sandthe horizontal lines associated with thesymbolic boires ofFig. 3a.

Reference is'now madeto' Fig. 4;whe'i'ein h'e're ispre- 'sented atypicahcompl'ementer or complementary signal generating networkcircuit610 adapted for operation as any-one of thecomplenientercircuitsCobf FigQl, the remainder of the complement circ11its'CobtFig. 1being a'duplicatethereof. "The complementary"signal-generator network610 is 3 responsive to binary 'ortwo-level voltage control signalsapplied at afir'st'inp'ut terminal 612 for selectively gating or-passingan electrical pulse or clock signal applied at a secondinputteritninalf614 to produce two complementary electrical pulse"output signals at a first'output terminal 616 and a'second outputterminal 618,"respective1y.

Complementary signal'generating network610 includes first'and secondelectronic gating circuits-620 and 622, respectively, responsive todifferent predetermined voltage levelsof the;applied control signal fors electively presentingtheapplied electrical pulse signal at outputterminals 616 and-618, respectively. Firstgating circuit 620 includes apair of unidirectional current devices, such as crystal diodes 624and'626, the cathode of 'dio'de 624 being connected to inputterminal"614 and the-cathode of diode 626 being connected to controlterminal 612. Diodes 624 and'626 have their anodes 'cor'iiiectedtogether at a common junction 628*whichis connected to output terminal616. "Common "junction 628 is also coupled to one terminal'B-lof asource-ofb'iasing potential, not shown, by a biasing resistor 630, theother terminalof the source being grounded. Second gating circuit 622also includes a pair of serially connected unidirectionalpurrentdevices, such as $t du es-.631 and E fLaiQ E Q J Q H .FQWHQH junction628 with output terminal 618, the cathode of Sa aa Fzand,

I to the voltages 'E 'and E a udthelo utput leadi405 and by a i 10. t v

the biasing potentialstat terminals 3+ and E and typical "values thereof'will he described in detail below; For reasons which will become moreclearly understood later, however 'it should be stated that thepotential appearing geisha tedlito common j unction 628 and.anojaehffatoat 3 4 b eing connected to output terpotenti 'al,notfshovjufby a biasing resistor "640. In a similar manner, diode 63.4.has its anode coupled to one ffa source of biasing potential, notshown,k g riesisl'tori642. The other terminal of each of the sources isconnected to ground. The function of at termiiial E is lower than thepotential at terminal B+. In .operation, input terminal 614 is connectedto i a source/"644 ojrj' n'eg'ative electri'cal clockpul'ses Cpto beselectively passed, and control terminal 612is .connectedtofayariahle'potential control or binary'signal source, such asasquarewave signal source 646 which controls the'selectivity' offga tilg circuits 620 and 622; Source 646 may beany suitable source of asignalhaving alternate relatively high and relatively low voltagelevels,

such as .a conventional voltage state gating matrix.

" Referring now to Fig. 4a, there is shown a 'composite diagram of thewaveforms appearing at various} points in the'complernentary'signalgenerating networkot Fig. 4.

The control signal, generally designated "647, which is i applied tocontrol terminal 612 from sourceT646fincludes alternate relativelylowand high ,voltage levels: E and E respectively, thevoltage level E correspondingsub- "'stantially to the biasing potentiahat'terminal Thenegativeelectrical pulse or clock signal (2p, generally desi'g'fiated6:45,. which is applied to input terminal @614 from source 644, has asteady state voltage,'l'level" which is preferably substantially equalto potentialE periodically recurring negative pulse excursionstofisignal64S lowering the potential of the signal accordingly.

Assume now that'signal 647 is initially'at its low potential value ofE2, as shown at timeftji n Fig. 4a.

Under'th'e'se conditions the signal, gene rally' desigriated 629,appearing at common junction 628will be;at,a voltage level substantiallyequal to level E due to the clampmg action of diode 626. 'In' a similarmanner, the

si nal, generally designated as 637 appearing at common jjunction v636,will 'h'ave a potential value substantially equal to'E due to theclamping action ofidiode 632.

Consequently, the potential difference across diode 634 tnsecond gatingcircuit 622 is substantially 'iero volts, whereas diode 624 in firstgating' circuit 620 is backbiased by substantially the voltagedifferential between "the voltage levels E and E "Consider now thebehavior of complementary signal generating network 610 when signal 645includes a first negative pulse 645a, the pulse amplitude being equal toor less than thevoltage differential between voltage levels E and ESince the amplitude .of 'pulse 645a insufiicientto drive thecathode ofdiode 624 below voltage level E it is apparent that diode 624 willremain back-biased. Accordingly, diode 624, will notpass the negativepulse to common junction 628 and hence to output terminal616,

When negative pulse 645a is applied to input terminal 614, the potentialof common junction 636,,heretofo're clamped substantially at level E bydiode $632, will be lowered accordingly, due to the coupling action orcapacitor'638, It is cle'ar of course, that dio de 632 will theimmediately back-biasedior the duration lof pulse 645 i1 ,jsin ceitsc'athojde is held substantially. at levelili;

"anode Wlll fall below potential E by approxiiriatelyt'he due toftheclamping action of-diode626a' whereas it's amplitude of pulse 645a.It'fo1loWs then, that pulse 64511 is inhibited fromappearingtat outputterriiinal 616 y back sed d s'f wa d $632.

It clear, Hana/a; that made 634 is" hew'ffcnthiased by the applicationofpulse 645a since the potential of common junction 636 and hence thecathode of diode 634 is driven below the voltage level E; by themagnitude of the applied pulse. Accordingly, negative pulse 645a will bepassed by diode 634 and will result in a corresponding negative pulse619a in the signal, generally designated 619, which appears at outputterminal 618.

Assume now that signal 647 swings to its relatively high level potentialvalue E and" that signal 645 is at its-steady state level E Under theseconditions, the potentials at commonjunc'tions 628 and 636 also swing tovoltage level E due to the clamping action of diodes 626 and 632,respectively. Consequently, the potential difference across diode 624 infirst gating circuit 620 is substantially zero, whereas diode 634 insecond gating circuit 622 is back-biased by substantially the voltagedifferential between the voltage levels E and E I Let us now assume thatsignal 645 includes a negative pulse 645b, the amplitude of which isequal to or less than the voltage differential between voltage levels Eand E It is immediately clear that diode 624 will be frontbiased andwill, therefore, pass pulse 645b and produce a corresponding outputpulse 629!) in signal 629 appearing at output terminal 616.

Although pulse 645b is also applied to common junction 636 by couplingcapacitor 638, it will be noted that the pulse 637b appearing in signal637 does not lower the potential of common junction 636 below potentiallevel E Accordingly, diode 634 will remain back-biased and therebyinhibit the applied negative electrical pulse from appearing at outputterminal 618.

If signal 647 applied to control terminal 612 of complementary signalgenerating network 610 again swings to its low potential value of E; asillustrated in Fig. 4a, a negative pulse 6450 applied to input terminal614 will again produce a corresponding negative pulse 619a at outputterminal 618 and will be inhibited from appearing in signal, 629 atoutput terminal 616. It is clear, therefore, that complementary signalgenerating network 610 is responsive to the relatively high andrelatively low potential levels of control signal 647 for selectivelypassing negative electrical pulses applied at input terminal 612 toproduce two complementary output signals at output terminals 616 and618, respectively. In other words, an applied electrical pulse signalwill be presented at either output terminal 616 or at output terminal618 depending upon whether control signal 647 is at its relatively highpotential value or its relatively low potential value, respectively.

As set forth above, diode 626 and resistor 630 are utilized for clampingcommon junction 628 at substantially the instantaneous voltage ofcontrol signal 647. However, diode 626 also performs the additionalfunction of inhibiting electrical pulses appearing at junction 628, suchas pulse 62% in signal 629, from being applied back into squarewavesignal source 646. For example, when electrical pulse 645b is applied atinput terminal 614, the potential of common junction 628 drops below itsclamped potential level E, by the voltage amplitude of pulse 62911.Since the potential E is being applied to the cathode of diode 626 atthis time, diode 626 is back-biased for the duration of pulse 629b,thereby eifectively isolating source 646 from clock pulse source 644.The combination of diode 626 and resistor 630 may, therefore, be termedan isolating network,

It will be recognized by those skilled in the computer .art that ifsquarewave signal source 646 comprises 2. voltage state gating matrixhaving a conventional diode and gate output circuit, the isolatingnetwork including diode .626 and resistor 630; may be eliminated fromcomplea 10 and the isolating network may be excluded from complementarysignal generating network 610.

The abovedes cribed complementer or complementary signal generator isfully described and claimed in copending U.S. patent application, SerialNo. 308,045, for Complementary Signal Generating Network, byDa'niel L.Curtis, filed September 5, 1952, now Patent No. 2,812,451.

The structure of the gating circuits providing the input signals fortrigger circuit F (1,3) and the various flip-flops which are included inthe embodiments of Fig. 1 are defined according to certain Booleanalgebraic equations which specify the sequences of stable states of thecorresponding: flip-flop or trigger circuit. Before considering thespecific mechanization of the gating circuits illustrated in Fig. 1,therefore, it is essential, for a complete understanding of theinvention, to consider the basic algebraic equations which define thegating circuits. It will be noted thatthe variables used in thefollowing equations correspond to the electrical signals indicated inFig. 1, so that each equation defines an electrical function of theembodiment shown.

Logical Boolean algebraic equations will be frequently employed in thisdiscussion for explaining the mechanization of circuits employing andand or circuits or gates which correspond directly to the logicalequations. Such circuits are well known in the art, typical circuitsbeing described in detail in U.S. Patent No. 2,644,887, filed December18, 1950, entitled Synchronizing Generator by A. E. Wolfe, Jr.Regardless of structural variations, the functional characteristics ofthese logical circuits remain substantially constant in the art, i.e., alogical and circuit produces an output signal only when signals aresimultaneously applied to all the inputs, and a logical or circuitproduces an output signal when a signal is applied to at least one ofits inputs. I

With 3-input variables A,, B,, and X,, we may define functions F, and F,indicating when 1 or 3 of the variables A,, B,, and X, are 1, and when 2or 3 of the variables are 1 according to the following Boolean algebraicexpressions:

In these equations the dot indicates the logical and and the plus thelogical non-exclusive or; so that the function A,.B, indicates that ifboth A, and B, are 1, A',.B, is 1, and 2 or 3 of the input digits A,,B,, and X,- must be 1. Similarly, A,.X, and B,.X, indicate the othersituations where 2 or 3 input signals are 1. The complete function forflip-flop F (2,3), then, is the or function of the 3 conditions A,.B,,A,.X,, and B,.X, so that the function is 1 if any one or more of theseconditions is satisfied. In a similar manner the function for flip-flopF(1,3)' is 1 if any of the conditions: A,I?,.X,; K,.B,.X,; Z,.1?,.X,; orA,.B,.X, is 1, indicating that 1 or 3 of the input signals A,, B,, andX, are 1. 7

With the variables F and P we may define any of the possible inputsituations, namely: all input signals being 0; 1 input signal being 1; 2input signals being 1; and 3 input signals being 1. The situations arerepresented as (0), (1), (2), and (3), respectively, and the definingequations appear as follows:

It will be noted that the situations (0), (1), (2), and (3) are defineddirectly as their binary equivalents in terms of the variables F and FThat is, the conditions 00, 01, 10, and 11 for F and F directlycorrespond to the binary numbers. While this separation of the t e itwhere X equals't'he weight of a binary "digit place j ofeach ofthe-inplit mimbersi lem me tal-tans torfsiniiiiifylng theanalysisfwhi'ch fgllows lshould be understood "notions may; beffitili'zed which do not "have 'a direct co'rfespondenbefto lia fyn jmb siifantpleyfthe 'flinctions F afiid fF ina 'be utilized to "define the'ihphtsituatians' follows:

git' in the jl"p'lace,' jv vhe re findica'tes the digit place 'viiithfspebt'to'the'iiipiltsignals. F iir ther'; since a carryover-one signalc -will ha've' a Rive'ight"doiible that of Keeping thee aveiaafiehhipeteamed; 51m h table derived, Table I below, expressingivaluesfor the variables Sb,-, C andC in termsot the variables;

C and C all have equal weights and F 'fihas a weight double that of eachof the variablesli f; C,- W In TableI, ayariable' represented 'by a 1level signal is indicated by thecligit land a'variable h representedby-a level signal by the digit 0. It; should be noted that a 0 in thetable, in a lditi nt indicating a 0 level signal, also indicates thatthe complement of the signal is'a llevel signal. 'Thus 'if 'the Valti ofvariable F} is indicated-"by a 0 in the table, this indicates thatsignal Ff is a 0 levelsignal and that signal F i'sa Il'vl signal.

T able 1 as dependentvaiiablesL on the 'lefthand edge 'Ofthe table is anadditional 'coliunn designatedTas tdtal weights. In this column, totalrelative wei'ghfof the binary 1's of 'each row' of section (a)of'tbeftable 'ate signalin the j b'inai yl digit position. "the' totalwei'g ht of the binary lsbfach rowjofsection (b) of the table is equalto the total weight ofithe' binary 1's on the same 1 as the midst'signific antsig nal.

Continging with an eiiplanation of the der iva tion fof the TableI, thenann er of detiving-thefdependent yariables of sectionstb) will no'w beexplained. Reihembeb ing that for any given binary digit place L thevalue or weight of the vari bles represented by signals Ff? will bedouble that of the weigh t of each pf the variables represented bysignals F 'G and G thetotal 1 digit in binary Table I divided'i'nto"thfee 'major*sections;indicated as sections (a), (b), and l(C),iespectively. Reading C are indicated at the top of the first, second,third,

Section (a) Section (0) Section (4:) t I Flip-Flop Independent Variables"Dependent Variables 01 Input v 1 Requirements 4 i, t. .1 Rules SignalsFP- F 01-1 05-1 C5 C5 "Sb," 1 i a "1C1 0C1 Relative Weights 2X- 1 1X 1X1X 4X 2X 1X Total weights: 7 t

0 0 1 0 0 0 0 I 0 1 0 0 0 ,1 0 0 1 2 0 O 1 0 0 fl 1 3 0 0 1 1 1 0 1 0 40 1 0 1 0 '0 0 1 5 o 1 i 0 1 0 1 i 0 6 0 i 1 1 0 0 1 0 ..7 0 1 51 1.1 ,01 1' -s 11 o 0 j 0 1 0 1 0 a; 9 1 1 0 '0 .1 0 1 1 10 1 0 1 I 0 0 l 1 11t y 1 0 1 1 1 0 0 12 1 V 1 0 0 0 1 1 13 1 1 0 1 1 0 V 5 0 L14 1 '1 1 1 01 0 0 ..'15 '1 1 1 1 0 '16 *relativdw'eights 15fthe indpiide 'nfvariables'foi'each i-hw or -'1 1'1le-ofsection (-a)f hiay -be 'leadilyobtained. "The total relative'weightsso derived are' ente'red in thetotalweights cc lumn.

s Thevalueofthe-sgm signal Sby=and 'thevcatryasig'nals C and Cf foreachlrule are then entered in section (b) 13 of the table in accordanceWill] the total weight of the independent variableson the "correspondingrow. For example, when all the independent variable signals'of section(a) are zeros, as in rule 1 of the table, all the dependent variables ofsection (12) must also be zeros. With reference to rule 2, the totalrelative weight of the independent variables of section (a) is.1X,whichis satisfied by making Sb, equal to 1 and C, and C, each equal to 0. Ina similar manner, the values of the independent variables of section (b)of Table I are derived for the remainder of the rules of the table.Thus, for example, noting rule 13, the total relative weight of thevariables of section (a) is 3X, which can only be obtained in section(b) of the table by making both Sb, and C, equal to l andC, equal to 0.V

As will be more fully explained later on, the symbols 1C1 and C1appearing at the top of the columns of section (0) of the table identifythe input requirements of the flip-flop C1. Briefly stated at present,101 and 0C1 indicate the input requirements of the 1 and 0 inputcircuits, respectively, of flip-flop C1, a 1 ma column indicating that atriggering or clock pulse must be applied to the corresponding input anda 0 in the column indicatingthat a triggering pulse must not be appliedto the input. A blank (neither a 1 nor a 0) indicates that a triggeringpulse is not necessary, but is permissible at the corresponding input.

By a comparison of the previous state of the flip-flop C1, as indicatedby the'value of signal C, with the desired .present state of theflip-flop, indicated by signal C,, the values for 1C1 and 0C1 may bereadily ascertained. Thus, when signal C, is 0 and signal C, is 1 for aselected row or rule, a triggering pulse must be applied to the 1 input1C1 of the flip-flop. When signal C, is 1 and signal C, is 0, a pulsemust be applied to the 0 input 0C1 of the flip-flop. This is illustratedby insertion of a 1 under column 1C1 and 0C1, respectively, on thecorrespondng rows or rules of the table. If

.signals ,C, and C, of a rule of the table are equal, no trigger pulseneed be applied to the inputs of the flip-flop,

but a 0 is added to the appropriate column of section (0) of the tableindicating that a triggering pulse affecting a change of state of theflip-flop must be inhibited.

Noting rule 3 of the table by way of'example, signal C, is 1 and C, is0, thus, a 1 is inserted under the 0C1 column heading indicating that atriggering pulse must be applied to the 0 input of flip-flop C1. As afurther example, consider rule 8. Signal C, is 1 and signal C, is 1,thus, it is not necessary to apply a signal to either the 1 or 0 inputof the flip-flop, but no signal is allowed on the 0 input as indicatedby a 0 in the 0C1 column. In this manner, the remainder of the valuesfor section (c) of, the table areinserted.

From Table I above the dependent variables 8b,, C, and C, may beexpressed by logical Boolean functions interms of the independentvariables of section (c) of the table. Considering first the derivationof an expression for Sb,, it is noted that signal Sb, is a 1 levelsignal on rules 2, 3, 5, 8, 10, ll, 13, and 16, and a 0 level signal onall other rules. On those rules when signal F, is 1, i.e., rules 5, 6,7,8, 13, 14, 15, and16, signal Sb, is 1 only during the time that signalsC, and C, are both 1's (rules 8 and 16) or both Os (rules and 13). Thus,the logical Boolean expression defines signal Sb, for rules 5 8, 13, and16. In the above expression, the dot and parenthesis indicate thelogical Boolean and, the plus the logical Boolean asindicated by rules2;;3; 10,. and 11.

4 This maybe expressed in logical Boolean form as where the bar over asignal indicates, as previously,

the complement of the signal. By logically adding the above twoexpressions for Sb,,-a combined junction expressing all conditions forSb, may be written as:

The function for Sb may also be considered to be a 1 m3 function of thevariables F C, and C, which may conveniently be symbolized by thefunction G, (F,

C C, where G is introduced to indicate a function of other functionssuch as F, or F, In terms of the input variables A,, B,, X, and thebinary carries C, and C, we may also express the sum Sb as the It shouldbe apparent, then, that there are a considerable number of choices offunctions defining the sum Sb.

In a similar manner the binary carry function C, may be determined fromTable I to be expressed by the following function:

In observing Table I it is noted that 0, is 1 only when 1 is 1 (since atleast two input variables A,, B,, and X, are required), and that underthese conditions it is the complement of the variable C, so that C, maybe derived from C, as follows:

Before considering the mechanization of gating circuits 10F(1,3),10F(2,3), 10C1, 10C2, and 10Sb, it is necessary to understand,thegeneral form of equations utilized to define the input signals fordirect-current trigger circuits and flip-flops. The discussion here isbrief since the general theory'of flip-flop control functions isdiscussed in considerable detail in copending US. patent applications:Serial No. 327,567 for Binary-Coded Flip- Flop Counters, by E. C.Nelson, filed December 20, 1952, issued December 10, 1957, as Patent No.2,816,- 223; Serial No. 327,131, for Binary-Coded Flip-Flop Counters, byR. R. Johnson, filed December 20, 1952, issued September 23,1958, asPatent No. 2,853,238.

Three general types'of flip-flop or trigger circuit input functions maybe utilized to control the sequence of stable states of an associatedflip-flop or trigger circuit. According to one type of equation, thesequence of stable states of the controlled device are directly definedso that the value of the equation (1 or 0) at a particular time or,and'the bar represents the complement of the signaL' When signa1'l=, is0 in the table, signal Sb, is 1 .only when either signal C,' .0r C, is lbutnot .both,

a setting function.

indicates the desired setting. This type of function may be utilized todefine a voltage level signal which directly sets the associated triggercircuit, without delay. Where a flip-flop circuit is controlled withthis typeof-function the flip-flop assumes a stable state during thefollowing digit timeinterval irrespoddiiig to 'the -settiiig function ofthe previous tlrii' intl'y al. T

According to a second type of defining equation, the

conditions;"for't changing the flip-flflkystable state, or

triggering tlie flip -flop are established. When this type ofmechanization is utilized, a conventional flip-flop is lied to "both In-many situations, it'is desirablefttvseparait the changing typeof'*e'quati'dn -into two partialch angihg functions which separatelydefine the conditions for changing the associated flip-flop stablestatgfrom oyto l, -;a nd frorn' 1 to O. :The parti-ahchanging;functions" are particularly the flip-flop to be controlled. In this casethe partial-= "considered below and fully des ftioned op'ending'applieatibiis by' E.-C/; Nelsomand -R:---R. Johnson. I i

An convenient notational system niaybe employed 'for I and simplifiedpartial changing functions above defined. For example; in=the abovementioned' copending applications by R. R. Johnson and E. C.-Nelson, thesetting func- 1 letter (nb,, or n indicating theparticulariflipflopwhich is controlled, and either a 1 or 0;dependingupon whether thecontrolled flip-flop is to be set to the 1 or the 0 state, respectively,The changing functions are represented by the'ltter Clifdllbwedby'theiletter a,'b, n, and the partialchanging"functions-are"represented in the same'fr'iannef 'as thechanging functions with the addition of a 1 or 0 indicating whether theflip-flop is changed to 1 or. changed 1:00.. The simplified -partialchanging functions aredesignated;by=thelnumber 1 or 0 indicatingwhetherwthe functions define? signals appliedto the l'or '0 input oftheflip-flop, followed 'by-the ,letten'iA, 'B, or N representing theflip-flopcontrolled. 7

This application uses notations sirnilar generally to those previouslyused in the copendingvapplications by Johnson and Nelson. However,thisiapplication uses a diiferent'notationfor settingfunetions than thatused in the copending applications by Johnson and Nelson As willbecomeiapp'arent subsequently, a :fsettingTK func tibn r'nay be definedasfthat ,whichgtriggers;alflip-flop to utilized in thisrapplication',the-setting functionqforcsetting functions:

The setting-functionfor setting a fiip-flopto theil state is representedin this application by ,the symbol "T0- ,fol-

lowed by the letterA; B, fiop'c'ontrolled.

. or N? indicating the fiip hus the-setting function for setting awflipflopg to the'l' stateis 'designated by g thegnotation T01 the 113explained in the above-rne ntioned co-' f 'wh'i'ch may be rediicedtothe' simplifiedjparti al changing "516 1 G andH- beinganyrtfunctionsr.ofrlvariables other than F 'ed-in-the above menipflopFj. 11i erms bf algeb'raicvariablesthis relation- Jp la'ined'in theabove-mentioned copending application to J'. V.Blanken'bakerf thisrelationshipfn ay be utilized to From these principles" it I hould 'beapparent that} the variables, situation (0), it is notedthatlCPisalways0 the values 1 1, .jan'd Q oppositel-to-f the" positionswhere Tito 1, sinlc'e' in these =positions C assumes fand' thecomplernentary carry C the CF is ac;

It' is. convenientthen to reduce Table I intofa; separate section (0) ofTa'ble I is'derived with reference tothe 1 corresponding values ofjthe-variables CF and C these i'variables need jn o longer be consideredin determining rived by 'expres singtheyalu es for ICIfand'OGI in termsof, the remainin independent variables of secti'onfa) of Table I.ThusQthei l6'rules of Table I reduce to S ruIeS tions forthese vairiablesu Considering "the columiis of Table II from left to right, the firstcolumn of the table lists new rule nurnbers, the second column includesvalues for the variable--C, ,the thirdkolumn ineludes va'lues for thevariable P the fourth column' the: values" of for 1C1 and 0C1,respectivelyfand the seventh andflast column on the right identifiesthe-con spondingruie num bersi'of Table I above; a Table 'Ilis'derive'dby making a single row or rule-foreach case in Table "I whereinthevalues for F F and C are the s'ar'ne Fbr exanqiple, rules 1' and '3 ofTable l havethe same values for all independent variables ofsection 1)except tile values for C "which iseliminatd in'TableIl. Thusirlilesland} are cornbined as' rule 1 in Table'JI. Thefunctions lCl and 061arefth'edderived from Table II as indicated, v TH Table 111 p tA*'c'on1pleteset-of mechanization functionsdefining the where'signal Cpisintroduced as a final and condition 1 to synchronize the entry ofdigitsintothe flip-flops, one pulse Cp being applied each binary digittime of operation. No clock pulse is required to control direct-'current trigger circuit F(1',3). It will be noted that signal C,- isobtained from signals F,- E C,- and ("3 afterone delay, introducing atotal of two binary digit time delays as required. e

As has been previously mentioned and, is Well known in the art, thesignals impressed ontheinputsof a flip-flop don'ot afiectthe outputsignals of the flip-flop until one binary bit or digit time later. Thisis readily apparent from a' realization that a flip-flop is triggered bya'clock' pulse Op. The controlling gating circuit associated with a fiipflop provides two-level vo'ltag'e gating signals which control theapplication of clock pulses Cp to the inputs of a flip-flop. Thus, sincethe gating circuit 10612 of Fig. 1 controls the application of clockpulses C1; to the input circuits of flip-flo'pCZ in response to signalsE F C,- and (3 the output signalsof flip-flop C2 representing a functionof signals'land C,- and their complements will occur one clock pulse Cplater in time or at 7' 2 time. More 7 specifically, the signals F,-represent the signals F one clock pulse later, or expressed in anotherway, represent the value for the variable F in the next lowersignificant binary digit place. Similarly, signal C- represents thevalue of variable C, in the next lower order significant binary digitplace, where each signal is referenced in time or digit place to theinput signals F F and their complements. Thus, the output of flip-flopC2, appearing one digit time or clock pulse Cp later than the inputsignals to the flip-flops, rightfully are designated as"C,- indicatingthat the signals produced byflip-flop C2 represent the carry-over-twofunction C delayed two binary digit time intervals or clock pulses Cp.

As indicated in Fig. 1, each of the and" functions in the equationsdefining gating circuits F(1 ,3), 10F(2,3), 10C1, ltlCZ, and 10Sb (inthe corresponding equations shown above) is provided by an and" circuit,symbolically represented in thefigure as a dot en'-' 18 produce thedesired' input function 1C1. m et nization of the other functions shouldbe apparent from this example.

In order to illustrate the equivalence between the above describedsymbols for logical and and or circuits and actual circuits, 'a typicallogical and"circuit is shown in Fig. 5 and atypical logical or circuitis illustrated in FigI 6.

Referring to Fig. 5 there is shown a typical logical 'and'circuit 910'indicated by broken lines and having two inputs 911 and 912 coupled bydiodes 915 and 916, respectively, to a common junction 913 which isconnected by means of a resistor91'4 to a B+ supply, the

closed by a semi-circle, which responds-to signals applied to separateinput terminals and produces a l-r'eprese'nting" output signal only whenall input signals are l-r'epresenting signals: Thus, and circuits 1001-1and 111C1 2 in gating circuit 1001 respond to signals F 6, +F,- andsignals C F F respectively, to produce 1"- rep'resenting output signalsaccording to the and functhe or functions in the above equations isprovided with an or circuit symbolically represented in the figure witha plus enclosed by a semi-circle. Thus, the or function ('6 2 +I j isproduced by or circuit 1061-3; and the functions F,- .((7, +F, and C .F,.F, are combined in or circuit 1061-4 to common junction 9 13 forming asingle output. As indicated, input 911 is applied to the cathode ofdiode 915, and input 912 is applied to the cathode of diode 916, theanodes of both diodes 915 and 916 being commonly connected to theoutput'terminal 913. The logical and circuit 91ll'functions typically inthat a signal appears on output lead 913 only when signals are appliedsimultaneously to inputs 911 and 912. Where an additional input isrequired it maybe added to the circuit of Fig. 5 by the addition of anadditional diode connected to the common junction point 913 in a mannersimilar to that of diodes 915 and 916. In order to clearly illustratethe orientation ofthe input and output leads of a symbolicallyrepresented and circuit and the typical and circuit of Fig. 5, asymbolical representation. of an. and

cir'cuit'is' illustrated in Fig. 5a; It should be noted that" the inputsand outputs associated 'with the circuit. of'Fig, 5' and thesymbolically represented logical and circuit of Fig. 5a aresimilarly'orientated.

Reference is now made to Fig. 6 wherein there is illustrated a typicallogical .or circuit 920 indicated by broken lines and having two inputs9 21 and. 922coupled by diodes 924 and 923, respectively, to a commonjunc tion 925 which is connected by means of a resistor9 26 to ground,the common junction 925 forming the single output. to the anode of diode924, and input 922 is applied to the anode of diode 923, the cathodes ofboth diodes 923' and 924being commonly connected to the outputterminal'925. The logical or circuit 920 functions typically in that asignal appears on output lead 925 when a'signal' is" applied to eitherinput 921 or input 922, or both; Where an additional input is required,it may beadded' to the circuit of Fig. 6 by the addition of anadditional diodeconnected to the common junction point 925m a mannersimilar to that of diodes 9'23 and 924. Again" it" should be noted thatthe inputs and outputs associatedwith the circuits of Fig. 6 andasymbol'ically represented logical or circuit of Fig. l are similarlyorientated in Fig. 1. In Fig. 8a there is presented a symbolicrepresentation of the logical or circuit illustrated in Fig. 6,

wherein the inputs 921 and 922 and the single output 925 of Fig. 6 isprovided with similarly orientated leads in Fig. 6a. 7

The operation and characteristics of the logical; and" circuit 910 ofFig. 5 and the logical"or circuit 921} of: Fig. 6 are fully described indetail in the above-mentioned Wolfe patent, therefore, furtherexplanation of the circuits of Figs. 5 and 6 are not required here.

The operation of the binary sum producing circuits" ofthe embodiment ofFig. 1 will be considered after the binary-coded decimal correctioncircuits have been con sidered below; a complete binary-coded decimalsumming.

operation being illustrated wherein the true binary sum Sb is formedfirst and the desired binary-coded decimal sum Sd isderived therefrom.

As shown in Fig. l'the correction circuit includes flip flops F1 and F2which are controlled through gating circuits MP1 and 101 2,respectively. The desired bi:- nary-coded decimal sum is obtainedthrough output gating circuit '10Sd which produces a signal series Sdcorre-. sponding to the binary digits of the decimal sum. It

As indicated in the figure, input 921 is applied? also be noted thatassociated with the correction circuit is a flip-fiop'Cdm whichreceivesa'modified decimal carry Table III "20 F1 according to the technique.introduced in the copencling application by E. C. Nelson. l I i I ISectlonla) Binary Sum Digit Values Section Total 7 Weight Section (d)Decimal Sum Digit Values Section (c) I Decimal Section (2) Carry Digitson 04 sa sun sd Flip-Flop Input Requirements Rule i-n-nmooca-u-n-uococHOOHHOOt- HOOHHO O OHOHOHOI-IOHOHOHQ signal through gating circuit10Cdm. The function of flip-flop Cdm and, the associated gating circuitwill be more fully understood after the defining algebraic equations forthe decimal correction have been derived.

During the correction'time interval, as indicated by a signal T beingequal to 1, signals corresponding to the true binary result digits Sb Sband Sb are registered in flip-flops Sb, F2, and F1, respectively.Signals 'T and 'I are generated externallyand applied to the 3-inputbinary-coded, decimal adder of Fig. l to control the time of thecorrection operation of the adder, i.e., to control the time at whichthe second, third, fourth and fifth true binary sum digits asrepresented by signals Sb are corrected or converted to binary-codeddecimal form as represented by binary signals Sd. Arithmetic units suchas the 3.-input adder circuit of Fig. l are generally associated with,and usually forms a part of a digital computer. Signals T and '1 arereadily available in digital computing devices and are usually generatedwithin the computerby counting circuits responsive to clock pulses thusoperating as binary bit or binary digit counters. In

the. present instance, signals T and T. are 1 and 0 level signals,respectively, during the correction time interval ofthe adder of Fig. 1and have 0 and 1 levels, respectively, atall other times. At this timethe fifth binary digiLSb is a function of carry signals C and C and acorresponding signal is produced by gating circuit 10Sb. The function Sbmay be'derived from the general expression for 812 given above bysubstituting 0 and 1 for F5 3 and F since no binary-coded decimal digithas more than four binary digits. as follows: a

Sb5=T.(C .(74 +63 .C4

where the term C is obtained in the fifth binary position 1 thecombination 1, 1, 1, 1, for signals S12 Sb Sb Sb is omitted for section(a). This is because the maximum Sb may then be expressed possiblebinary sum'obtamable 18 '29, whereas the above by providing a value ofi=5 for C, and where the i term C is obtained in the fifth position byproviding a value of j==5 for C The correctionswhich are required areindicated in Table III below wherein all of the possible binary sums Vare considered with corresponding decimal digit variables. The variablesSd Sa' and 8:1 are the desired second, third, and fourth binary digitsof the decimal sum digit and the variables Cd, and Cd,- correspond todecimal carries-over-one, and decimal carry-over-two,respective- 1y. Itwill be noted that digits S11 and S 1 are produced and simultaneouslyshifted forward into flip-flops F2 and '4 GM m1 on QHH4OHO HHHD- HOOOOQQOOO OOoOOHt-u-u-n-oooco HOOOOHQCOOPOOOO ov-nocor-ucocn-ucoONOHQOHOHOOl-Qt-O O O b- O o H Table III is comprised of five sections,sections (a),

r (b), (c), (d), and (e), respectively. Section (a), designatedgenerally as binary sumdigit values includes a second, third, fourth,and fifth binary sum digit column Sbg, 8b,, 8b,, and Sb respectively.Section (b) includes a total weight column indicating the total weight10f the binary sum digits of section (a) for each row of the table,section (0) identifies the fiip-flop input requirements for flip-flopsF1 and F2 and includes columns 0P1, lFl', 0P2, and 1P2. The rows of thetable are identified as rule numbers in the extreme right hand column ofthe table. The digit variables, the digits, andthe weights of r thevariables are indicated at the head of each column of sections (a), (c),and (d).

Table III is constructed in the following manner. All possiblecombination of variables Sb S6 8b,, and Sb are entered in thecorresponding columns of section (a). This is accomplished by the samemethod utilized for constructing section (a) of Table I in that all 0'sare entered for rule 1 andthe values for each subsequent rule obtainedby adding a binary one to the least significant variable of sectionta),i;e., Sb It should be noted that rule having a total'weight,.asindicated in sectionfb), between 10 and 19; and entering a binary 1 inthe carryover-two column Cd for each rule witha total weight between20and.29.qSection (d) of thetable isobtained by entering the binary valuesfor digits Sb 8b,, and Sb in the corresponding rows of columns Sd S11and 8d of section (d) for total weights of 0 to 9, inclusive. For

total weight of 10 to, 19, inclusive,'and 'for total'weights from 20'to29, inclusive, the same values for Sd 8:2 S11 as'utilizedfor totalweights ofOto 9 are repeated: 1

Inexactly the same manner as the values for columns 1P1 and F1 ofsection (0) of Table I are determined, the values for columns lFl, 0P1,1P2, and 0P2 are obtained for section (0) of Table II. Thus, the valuesfor columns 1F 1 and 0P1 are obtained by a comparison of the previousstate of flip-flop F1, as indicated by signals F1 of section (a), withthe present state of the flip-flop as indicated by signals F1.Similarly, the previous state of flip-flop F2 is compared with thepresent state of the flip-flop by examination of signals F2 and F2,respectively, to determine the values for columns 1P2 and 0P2 of section(e).

The input requirements 1F1 and 0F1 of section (0) of Table III areexpressed in terms of variables or binary digits S17 Sb and S11 in TableIIIa below, wherein the corresponding rules of Table III are representedon the extreme right hand column of the table, the rules of Table IIIaon the next column to the left, lFl and OFl columns in the third andfourth columns, respectively, from the left, and the digits or variablesS11 Sb and S12 in the third, second, and first column from the right ofthe table. Under the variables S11 8b,, and Sb are the signals F2, Sb,and (C .'C',- +6 .C respectively, representing the variables.

The input requirement 1P2 and 0P2 of section (0) of Table III areexpressed in Table IIIb below in terms of the digit variables Sb 8b,,and Sb As in Table 1111:, the corresponding rules of Table III arelisted in the extreme right hand column of Table H111 and values for 0F2and 1P2 are included in the third and fourth columns from the right bandedge of the table. The S11 Sb and Sb columns appear at the third,second, and first column from the left hand edge of the table.

Table IIIa D Sb sb Sb lgits s 4 a R 1 R8116 fIfI lFl OFl u e Ta eSlgnals g H Sb r2 l i-2 :l

0 0 0 0 1 1 1 and 2. 0 0 1 1 0 2 3 and 4. 0 1 0 0 1 s s and 6. 0 1 1 0 04 7 and s. 1 0 0 1 1 5 9 and 10. 1 0 1 0 1 e 11 and 12 1 1 0 1 0 7 13and 14 1 1 1 0 s 15.

Table IIIb Dig Sb Sb Sb 5 4 2 1 R 1 'r iii fir lFl 0F 11 e a e SignalS-Z Sb F1 i' i2 i-1) 0 0 0 0 1 1 1 and 3. 0 0 1 0 1 2 2 and 4; 0 1 0 1 1 35 and 7. 0 1 1 0 1 4 6 and 8. 1 0 0 0 1 5 9 and 11. 1 o 1 1 1 6 and 12.1 1 0 0 0 7 13 and 15 1 1 1 0 s 14.

will satisfy rules 6, 7, and s. sb is 0 and sb is 1 for rules 9 to 15,inclusive. However, only rules 9 and 10 have the combination 572 311 811thus, the function Cd =S'b .1b .Sb satisfies rules 9 and 10. Bylogically adding the two above discussed functions for Cd the functionsCd =Sb .b '(Sb +Sb )+Sb .tb .Sb is obtained. Substituting thecorresponding signals for the variables in the above expression, theresult becomesf By well-known principles of Boolean algebra, the aboveexpression reduces to which, if the time signal T is added, agrees withthe equation for Ca above.

In the same manner, the functions for 1P1, 0P1, and 1F2, 0P2 werederived from Tables 111a and H111, respectively, reiteration of thestep-by-step procedure being deemed unnecessary at this point.

It will be noted that during the correction time interval (T=.1) gatingcircuit 10Sb already produces the digit S11 so that an additionalcorrection must be performed in order to introduce the decimal carrysignal Cd into the function for S12 In a similar manner, it is necessaryto modify the binary digit Sb so that it includes the decimal carry CdIn the embodiment of Figure 1 this is done by forming a modified decimalcarry signal Cd which is 1 whenever the true binary carry signals C andC represent a carry which is less, by 1, than the desired deci malcarry. Thus, Cd is l for numbers 10 through 15 since no binary carriesare formed and a decimal carry of 1 is required. A similar situationarises for numbers 20 through 29 since a digit 5b,; is formed(indicating that the function C .C" +'6 .C is l), but a decimal carry of2 (10 in binary notation) is required. The variable Cd therefore'is adecimal carry which may be added to the next binary-coded decimal digitseries in order to correct for situations where the true binary carriesare lacking in carry-over by l.

Reference to Table 111- indicates thatthe signal Cd may be defined asfollows:

The signal Cd may then be added to the signal series I remain 1,indicating a carry, as long'assignal Sb is 1- the setting function forflip-flop Cdmis defined so that the flip-flop is set to 1 by thefunction for Cd and remains 1 as long as-Sbcontinues tobe 1v The gatingfunction for circuit-.IOCdm ma'yfthus be defined as follows: 1

(10Cdm) tCdm=T.[Sb.(F I-F where the signal C is the output'signal offlip-flop Cam and is equal to the variable Cd after the correction timeinterval (T=1), but becomes a carry signal for the remainder of theperiod if Sb remains 1.

The true binary sum is then modified to include the decimal carry signal0- as follows:

W am-Hem],

A complete set'of equations defining the embodiment of Fig. 1 may thenbe written as follows:

A typical operation of the embodiment of Fig. 1 is illustrated in TableIV illustrating the addition of binarycoded decimal numbers 1097, 574,and 935. The signal T is shown indicating the digits which are availableduring the correction time interval.

In analyzing TableIV'it will be noted that lthe signals C 0 and F, neverassumethe combinationsf 101 or 110 since whenever signal C is 1 theprevious carry-over-one signal C is 0 and F,- is 1. As a result, anycarry formed (C,- at that time is equal to the signal F or the carryresulting from the presence of two or three input signals. The signal Sbis introduced in order to indicate the efiect of the addition of thedecimal correction signals 0 It will benoted that the decimal digits Sdare shown as being produced directly from the Sb digits without delay.In the actual circuit, it will be understood, signals Sd are delayedthree digit time intervals through the correction circuit.

It will be noted that the defining algebraic equations considered abovehave been written in various forms, illustrating the fact that thegeneric concepts herein considered are independent of the particularassociated set of equations. Thus, setting, changing, and simplified:partial-changing flip-flop functions may be utilized interchangeablywithout departing from the invention. It will also be understood thatthe type of storagedevice utilized, whether flip-flop or triggercircuits, is generally immaterial. Trigger circuits:F(1,3) and F(2,3) j,for example, may be replaced with flip-flop circuits, introducing abinary digit delay in the adder operation.

At attempt has been made to point out a few of the important variationsin the correction methods and methods of obtaining' the arithmeticcombination of at least As used in the specification and in the claims,the term arithmetic is intended tocover.

three input numbers.

mathematical operations such as addition and subtraction which arecapable of being completed in a single cycle'of computation rather thanin a plurality of cyclesof computation such as for multiplication anddivision. These arithmetic operations produce a binary result Rb whichcorresponds to the binary sum Sb in Figure 1 audio the The arithmeticoper-' equation (lOSb) set forth above. ationsalso produce abinary-coded decimal result Rd which corresponds to the binary-codeddecimal sum Sd in Figure 1 and to the equation (d) set forth above.

It will be understood, however, that each of the variations mentioned inthe previous paragraph as well as those apparent to a person skilled inthe art leads to a multitude of others which may be considered to be ofthe same general class. Because of this, the invention may be defined ingeneral terms.

What is claimed as new is:

1. A multiple input arithmetic unit for performing an arithmeticoperation capableof being completed in a single cycle of computation andfor performing such arithmetic operation upon N binary-coded decimalinput numbers where N is an integer greater than 2 and for performingsuch arithmetic operation to form a binarycoded decimal result, theinput numbers being represented by N corresponding electrical inputsignal series and the binary-coded decimal result being represented byan electrical output signal series, respectively; said arithmetic unitincluding? first means responsive to the N-input signal series forproducing first series of signals indicating the results of thearithmetic combination'of the binary. signalsin each correspondingbinary position of the N input signal series; second means coupled tothe first means and responsive for each binary positionto the firstseries of signals and to the signals produced by the second means forproducing a second series of signals indicating the carries resultingfrom the arithmetic combination of the binary signals in successivebinary posi-- tions and the binary carry signals from preceding binarypositions; third means coupled to the first and second means andresponsive to the first and second series of signals for producing athird series of signals indicating the true binary result of thecombination of the N input numbers in each binary position and the carryof the arithmetic combinations from the preceding binary posi tions; andcorrection circuitLmeans coupled to. the first,

second and third means andresponsive tothefirst, second and-third seriesof signals for producing the output signal.-

first means includes first gating circuit means responsive to the inputsignal series for a value ofN=3- to produce first binary control signalsindicating when first pluralities of the N input signals have aparticular binary value for each binary position and'wherein the firstmeans also includes second gating circuit means responsive to the input"signal series for a value of N =3 to produce second binary controlsignals indicating when second pluralities of the N input signals havethe particular binary value for each binary position.

3. The arithmetic unit defined in claim 1 wherein said first meansincludes first gating circuit means responsive to the input signalseries for a value of N=3 to produce, in the first series of signals,first binary control signals indicating when first particularpluralities of the binary input signals have a particular binary valueand wherein the first means also includes second gating circuit meansresponsive to'the input signal series for a value of N :3 to produce, inthe first series of signals, second binary control signals indicatingwhen second particular pluralities of the input signals have theparticular binary value and wherein the second means is constructed toprovide binary carry-over-one signals indicating a binary carry of onefrom a first binary position to the next binary position and to providebinary carry-over-two signals indicating a binary carry of one from afirst binary position to a third binary position two positions higher indigital significance than the first binary position and wherein thesecond means includes first circuit means responsive to the first andsecond binary control signals for producing in each binary position thebinary carryover-one signals in a pattern dependent upon the occurrenceof the first and second binary control signals and the binarycarry-over-one signals from the first preceding binary position anddependent upon the binary carry-overtwo signals from the secondpreceding binary position and wherein the second means includes secondcircuit means'respo'nsive to the first signals from the first circuitmeans and responsive to the binary-carry-over-one signals for producingin each binary position the binary carry-over-two signals in a patterndependent upon the occurrence of the second binary control signals andupon the'binary carry-over-one' signals from the first 'preceding binaryposition. I

4. The arithmetic unit defined in claim 3 wherein said third meansincludes a binary result-producing network responsive to the binarycarry-over-one signals and to the binary carry-over-two signals and tothe first binary control signals and the second binary control signalsfor combining these. signals in a particular relationship to produce thethird series of signals indicating the true binary result of thearithmetic operation.

5. The arithmetic unit defined in claim 4 wherein the binary-codeddecimal correction circuit means includes first gating circuit meansresponsive in each binary position to the third series of signals andresponsive to the first and second binary control signals and to thebinary carry-over-one signals from the first preceding binary positionand responsive to the binary carry-over-two signals from the secondpreceding binary position for combining these signals in a particularrelationship to produce the output signal series representing inbinary-coded decimal form the arithmetic combination of the inputnumbets.

6. An arithmetic unit for performing an arithmetic operation capable ofbeing completed in a single cycle of computation and for performing sucharithmetic operation upon at least three binary-coded decimal inputnumbers to form the corresponding binary-coded decimal result, the inputnumbers being represented by electrical value in the binary position j;second means coupled to said first means and responsive to the first andsecond signal series and responsive to the signals produced by thesecond means in particular positions having a digital" significance lessthan the position for producing a third series of signals to indicate ineach binary position j the binary'carries resulting from the arithmeticcombinationof the signal series A,-, B and X,- in each binary positioni" and the carry signals in particular positions having a digitalsignificance less than the position 1'; and third means coupled to thefirst and second means and responsive to the first, second and thirdseries of signals for producing a fourth series of signals indicatingthe truebinary result Rb,- of the arithmetic combination of the" signalseries A,-, B,- and X and correction circuit means coupled to the first,second and third means and responsive to the first, second, third andfourth series of signals for producing the signal series Rd.

7. The arithmetic unit defined in claim 6 wherein the first means areresponsive to the input signal series A,, B, and X; in a particularrelationship to produce signals F and F in accordance with the logicalequations Fi =14 .Bj.X +A .B ..X +A5-Ej-X +Aj.B -Xj i i' i+ i' 1+ i- 1where the dot represents an and relationship and the plus signrepresents an or relationship and where'the bar over a term indicates acomplementary state of operation and where the signals F representthefirst series of signals and indicate the occurrence of one or threebinary signals A,-, B,- and X, with a binary value of 1 in the binaryposition j and where the signals F represent the second series ofsignals and indicate the occurrence of two or three binary signals A,-,B; andupon the binary carry-over-one signals C,- produced in theposition (j-1) of immediately less digitalsignific'ance than the binaryposition and wherein such second means are constructed to produce binarycarry-over-two signals C in each binary position and wherein suchsecond,

means are constructed to produce the binary carry-oven one signals C,-in accordance with the logical equations [F723. (C7' 22+F7-1'3) +'0 2 -F.F where the signal Cp represents a clock signal and where the signals1C1 and 0C1 represent input signals to the input terminals of theflip-flop C1 included in the second means to respectively obtain theproduction of signals C and (3 and where the signals C and C, representthe binary carry-over-two signals produced in the binary position (j-2)of immediately less digital significance than the binary position (j-l).

9. The arithmetic unit defined in claim 8 wherein a flip-flop C2 isincluded in the second means to indicate binary carry-over-two signals Cand wherein the second means are constructed to produce the binarycarry-overtwo signals C in the C2 flip-flop in a pattern dependent 27upon theoccurrence of the signal series -F2,3 and{C, and in accordancewith the logical equations:

1C2=F .'(7 .Cp C2: (F, +C .Cp

where the signals C represent a binary carry of one from each binaryposition j to the binary position having adigital significance of 2binary positions greater than the position j and where the signals 1C2and 0C2 represent input signals to the input terminals of the flip-flopC2 included in the second means to respectively obtain the production ofsignals C and (1, and where the signals C and C represent thebinary-carry-overone signals produced in the binary position (j-l) ofimmediately less digital significance than the binary position 1'.

10. The arithmetic unit defined in claim 9 wherein a flip-flop Rb isincluded in the third means to indicate the signal series Rb and whereinthe third means includes a binary result-producing network for producingthe signal series Rb in the Rb flip-flop, said binary result producingnetwork being constructed to produce the signals Rb in accordance withthe logical equations:

11. The arithmetic unit defined in claim 10 wherein said correctioncircuit means includes first and second correction flip-flops F1 and F2producing complementary output signalsF F and F F and having inputcircuits 1P1, 0F1'; and 1P2, 0P2, respectively, said correcrectioncircuit means also including first electrical gating circuits responsiveto signals F and F for producing said signal series Sd, secondelectrical gating circuits inv terconnecting said correction flip-flops,and third electrical gating circuits connected to said second correctionflipflop to provide input signals to the input circuits of said secondcorrection flip-flop.

12. The arithmetic unit defined in claim 11 wherein all binary-codeddecimal corrections are performed during correction time intervalsrepresented by pluralities' of clock pulses Cp and wherein signals T areproduced during particular clock pulses of each correction time:intervals and wherein signals '1 are produced during the other clocksignals of each correction time interval to obtain a repetitive patternfor the production of the signals T and 'I; the signals '1 representingthe-complement of the signals T, and wherein said correction circuitmeans further includes carry correction means and a carry correctionflip-flop Cdm for producing decimal carry signals Cd and Cd the signalsC representing the complep v p g p High Speed Computing Devices byEngineeringj where the representation toCdm indicates that the carrycorrection flip-flop is triggered or maintained in a state for theproduction of the signal Cd and wherein the correction circuit meansfurther includes means constructed to produce signals Sb and Sbrepresenting a t modified result of the true binary sum in accordancewith the logical equations: v

where the signals lF2i-and 0P2 are respectively introduced to the inputcircuits of theLflip-flop F2 to obtain the pro duction ofthesignals Fandji, the signals 1 representing thecomplementof the signals F andwhere the representation toFl indicates signals introduced to theflip-flop. FLfor triggering and maintaining the flip-flop F1 in the Fstate, the signal F1 representing the complement of the signals F1: andwhere the signals Sd indicate, the values in'successive binary positionsof the binary coded decimal result and where the first electrical gatingcircuitin the correction circuitlmeans are constructed to: produce thesignals sd and where thetthird electrical gating circuits in thecorrection circuit means: are constructed to produce the signals 1P2 and0P2 for introduction to: the i'nputcircuits of the flip-flop F2 andwhere the second; electrical gating circuits. in the correction circuitmeans are constructed to control :the'introduction: of input signalstothc input circuits of the flip-flop FL Reterences Cited in .the fileof thisl" it t FOREIGN PATENTS 678,427 I Great; Britain Sept; j 5.11952IQTHE'R REF E k Research Associates, McGraw-I-lill, 1950,pages 289-293,"

UNITED STATES PATENT OFFICE Certificate of Correction Patent No.2,923,474 February 2, 1960 Mn Virgil Blankenbaker It is hereby certifiedthat error appears in the printed specification of the above numberedpatent requiring correction and that the said Letters Patent should readas corrected below.

Column 15, line 21, for An read -Any; column 17, line 17, the equationshould appear as shown below instead of as in the patent:

column 21, Table IIIb, the fifth and sixth vertical columns should beheaded, respectively, 1F2, and 0F2, instead of as in the patent; line64, the equation should appear as shown below instead of as in thepatent:

0d =T. [5 .5 .5'b.(F +F (0 +0 fif column 22, line 7, before the equationbeginning with F insert a line 24, the equation should appear as shownbelow instead of as in the patent:

36 36 .85 column 23, line 13, the equation should appear as shown belowinstead of as in the patent:

EZ O e/5'6 5W3? line 43, the equation should appear as shown belowinstead of as in the patent:

0F2= [T.F +T.(6 .5 +s b +F 1.0; Signed and sealed this 26th day of July1960.

Attest: KARL H. AXLINE, ROBERT C. WATSON, Attestz'ng Ofitaer.Oomwnissz'oner of Patents.

